13 research outputs found

    Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization

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    Abstract—This paper presents the design of an asynchronous cellular logic array for binary image processing algorithms based on wave propagation/collision in an excitable medium. The array consists of identical logic cells enabling the propagation and detection of wave-front collisions necessary for the object skeletonization. Low power, low area and high processing speed requirements were met by employing the asynchronous dynamic logic approach resulting in a processing time less than 0.45ns/pixel and energy consumption of less than 0.15pJ/pixel. The cell consists of 19 transistors and occupies an area of 7.5×6.3µm2 in 90nm CMOS technology. The proposed array could be used as a coprocessor in pixel-parallel SIMD architectures aiding the fast execution of medium-level image processing algorithms. I

    Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing

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    Tunable CMOS Delay Gate With Improved Matching Properties

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    Mismatch Compensation Technique for Inverter-Based CMOS Circuits

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    Tunable CMOS Delay Gate With Improved Matching Properties

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    Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems

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